1. Field of the Invention
The present invention relates in general to LSI and other semiconductor integrated circuits, a design method for the same, and a memory storing the program for executing the design method, and more particularly to semiconductor integrated circuit power supply lines, a pattern layout design method for the same, and a program storage device readable by a design system to perform the pattern layout design method.
2. Description of the Related Art
Recently, a tendency for a larger scale and a higher density of logic LSIs has increased an operating current flowing through the power supply lines on an LSI chip. The line width, on the other hand, has been reduced due to ever finer patterning, which would lead to, along with the increased operating current, a larger potential distribution caused by an increased resistance of the power line. A trouble which cannot be missed is that a portion of logic gates subject to a large potential distribution suffers from a slow operation speed and malfunctioning. A conventional countermeasure against the potential distribution is an addition of supplemental power lines to the fundamental power lines directly connected to logic circuits.
FIG. 1 is a plan view for a conventional pattern of disposing contact holes and/or via holes in power lines within a logic LSI. FIG. 1 specifically shows, as an example of logic LSI, a power supply line combination of fundamental power lines 101 disposed in grid within a logic circuit and the corresponding horizontal supplemental power lines 102. In this example, each of intersections between the vertical fundamental power lines 101 and the horizontal supplemental power lines 102 has each via hole 103, through which those two types of power lines are electrically interconnected, to supply power to the logic circuits. The operating current flows through all the power supply lines within the circuit and to the power supply ring outside the circuit and then to the power supply pin. Since a potential distribution due to this operating current is proportional to a power supply line resistance measured from the center of the circuit to the outside the circuit, it becomes larger as it gets near the center of the circuit.
As shown in FIG. 1, the conventional logic LSIs have via holes disposed at every intersection between fundamental power lines and supplemental power lines. Actually, however, even with an arrangement of such supplemental power lines and via holes, potential distribution cannot sufficiently be suppressed, resulting in possible malfunction of the circuits.
FIG. 2 shows the potential distribution in the conventional logic LSI. This graph shows an actual potential distribution along a line parallel to the X direction (see, FIG. 1) through the circuit center CE, at which the voltage drops largest. This logic LSI has almost the same structure as the structure shown in FIG. 1, which comprises 300 vertical (Y-directional) fundamental power lines 101 in the first level layer, 100 horizontal (X-directional) fundamental power lines 101 in the second level layer, and 9 horizontal (X-directional) supplemental power lines 102 in the second level layer. Each of the supplemental power lines 102 is disposed for each 10 second layer (X-directional) fundamental power lines, having a width 10 times that of the second layer fundamental powerlines 101.
As can be seen from FIG. 2, the circuit center CE with the largest voltage drop is susceptible to an actual potential distribution down to a limit level (LV in the figure, e.g., 4.03V), at which the circuits may malfunction.